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11:00 - 11:20 |
Impact of Two-Step Recessed SiGe S/D Engineering for Advanced pMOSFETs of 32 nm Technology Node and Beyond |
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N. Kusunoki, N. Yasutake, M. Awano, I. Mizushima, H. Yoshimura, S. Yamada, F. Matsuoka |
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11:20 - 11:40 |
Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond |
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X. Wang, A. Bryant, O. Dokumaci, P. Oldiges, W. Haensch |
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11:40 - 12:00 |
Device Design and Scalability of an Impact-Ionization MOS Transistor with an Elevated Impact Ionization Region |
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E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, Y.-C. Yeo |
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12:00 - 12:20 |
A Prototype Wafer Processing TCAD Tool Composed of BMD Simulation Module, Metal Gettering and Thermal Stress/Slip Functions for Scaled Device Design Phase |
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T. Okada, A. Fathurahman, R. Takeda, H. Banba, H. Kubota, Y. Matsushita, M. Naito, S. Nakamura |
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12:20 - 12:40 |
Compact Modeling of Phase-Change Memories |
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K. Sonoda, A. Sakai, M. Moniwa, K. Ishikawa, O. Tsuchiya, Y. Inoue |
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12:40 - 13:00 |
Modeling of NBTI Degradation for SiON pMOSFET |
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J. Shimokawa, T. Enda, N. Aoki, H. Tanimoto, S. Ito, Y. Toyoshima |
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