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Mitiko Miura-Mattausch

Abstract

Title: Compact Modeling of the MOSFET Performance Distribution for Statistical Circuit Simulation
 
Variation of device performances is increasing according to aggressive scaling down of device sizes. It is therefore urgently required to correctly and efficiently include the device variations into circuit simulations. For realizing the requirement, two tasks must be accomplished. One is to develop methodologies to consider statistical variation effects without sacrificing simulation time. The other is to model the variations accurately based on their physical origins. Here we demonstrate that compact models based on the surface-potential description enable to realize accurate modeling of the variation in a similar way as 2D-device simulations. It is also shown how to extract variations of both the inter-die variation as well as the intra-die variation separately with use of basic analog circuits. The accuracy of extracted variations is verified in several different aspects. An investigation of three generations of advanced MOSFET technology reveals that the dominating origin of the performance variation is the impurity concentration. A methodology how to incorporate the variation into circuit simulation is also presented.
 

Bios

Mitiko Miura-Mattausch received the Dr. Sc. Degree from Hiroshima University. She joined the Max-Planck-Institute for Solid-State Research in Stuttgart, Germany as a researcher from 1981. From 1984, she was with Corporate Research and Development, Siemens AG, Munich, Germany, working on hot-electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of advanced MOSFETs for circuit simulation. Since 1996, she has been a professor in Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter at Hiroshima University, leading the ultra-scaled devices laboratory. She is an IEEE Fellow and is serving as an IEEE Distinguished Lecturer.