Abstract
Title: Integrated Circuit Variability – Modeling and Applications
IC variability has a hierarchical/hybrid character. Its hierarchy reflects the nature of IC production which can be viewed at the device, chip, field, wafer, and wafer-lot levels. It is hybrid, because at each of these levels variability consists of spatial, deterministic and random components. Finally, the sources of variability can be traced to interactions between layout components, modeling and manufacturing imperfections, as well as fundamental randomness at the atomistic scale. Consequently, capturing IC variability requires a concerted effort of test pattern design, data collection and TCAD simulations. This should lead to a complete, yet parsimonious statistical model, which can in turn provide suitable design guidance in order to ensure the optimal balance between yield and performance. This presentation will focus on the structure, characterization and use of such a comprehensive IC variability model, with an emphasis on applications around compact transistor modeling, and the efficient simulation of variability for various IC design applications.
Bios
Costas J. Spanos received the Electrical Engineering Diploma from the National Technical University of Athens, Greece in 1980 and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University in 1981 and 1985, respectively. In 1988 he joined the faculty at the department of Electrical Engineering and Computer Sciences of the University of California at Berkeley, where he is now the Andrew S. Grove Distinguished Professor and Department Chair. His present research interests include the application of statistical analysis in the design and fabrication of integrated circuits, and the development and deployment of novel sensors and computer-aided techniques in semiconductor manufacturing. He is also working towards the deployment of statistical data mining techniques for energy efficiency applications.