Abstract
Title: Statistical Compact Model Strategies, and Statistical Circuit simulation
The continuous technology scaling down to decananometer dimension scale has increased the magnitude of global process variations that define Interdie tolerance, and given rise to dramatic increase of local Intradie variations, both of systematic or random nature, as can be observed on individual Mosfet devices . Seen from IC design perspective, the margins needed to reach acceptable yield at circuit scale are being reduced both by the increased variations of the individual device characteristics, and by large scale integration environment constraints (Bias reduction to comply with Power dissipation or Reliability requirements, …). While considerable efforts are jointly made by the technology engineers to reduce Interdie and Intradie Process variations, and by the Design community to reduce Circuit sensitivity to, or compensate for, both deviations from Process or Operating conditions, it is expected that the Modeling engineers continuously improve accuracy and efficiency of modeling solutions in order to allow Designers to account for the impact of all sort of deviations on Circuits within the Design flow. In this area, the development of accurate Statistical Compact models capable to discriminate between all sorts of deviations, whether local or global, systematic or random nature, is a critical step to enable Design within specs with acceptable yield. The prime function of Statistical Modeling method is to elaborate interface that allow sources of variations observed in the technology to propagate into predictable variations of the Circuit performances figures estimated through means of Statistical Compact Model parameters and Monte-Carlo simulation. The presentation will highlight the principles of Statistical Modeling methods that can be inherited from Numerical techniques, the Industry practices in the field, and the development efforts that are supported by European community.
Applications of Statistical Simulation at Circuit level making use of Statistical Models will also be introduced (Design of Experiments and Response Surface Methods for Analog-Mixed Signal -RF circuit Design, Timing Analysis method (STA, SSTA) for System-On-Chip applications.
Bios
André Juge graduated with a PhD degree from Universite Scientifique et Medicale de Grenoble in 1981. He joined Thomson Semiconductors as Modeling Engineer to support Design applications in the field of emerging Bicmos technologies. In 1988, he joined Grenoble R&D center of STMicroelectronics as Modeling group leader for supporting Bicmos technology scaling from 2um to 0.7um generation. In 1994, he moved to Crolles R&D center as Compact Modeling team leader in charge of supporting core CMOS technologies from 0.5um down to 0.13um nodes jointly developped with Philips Semiconductors. From 2003 to 2007, he took responsability of Modelling department within Crolles2 Alliance, with the objective to meet common needs from ST, NXP, and Freescale design communities, within the development of core CMOS from 90nm, 65nm, and 45nm nodes. His current activities are devoted to: (1) Variability modeling for Circuit design, (2) Assessment of advanced device modeling solutions through cooperative projects with Academia and Compact Model Council (CMC).
