Technical Program


Thursday, September 1

Session 1:   Plenary Session (Diamond Room)
Chairpersons: N. Sano, Univ. of Tsukuba

P. Oldiges, IBM

9:00 Opening and Welcome Remarks

M. Hane, NEC Corp.
9:10
 Plenary: MOSFET Modeling beyond 100nm Technology: Challenges and Perspectives
1-1 M. Miura-Mattausch

Hiroshima Univ., Japan
9:55
 Plenary: TCAD Challenge in the Nanotechnology Era
1-2 M.D. Giles

Intel, USA
10:40
 Plenary: The R-Sigma Method for Nanoscale-Device Analysis
1-3 M. Rudan

Univ. of Bologna, Italy

11:25   Lunch


Session 2:   Bulk MOSFET (Diamond Room)
Chairpersons: H. Oka, Fujitsu Labs.

M. Profirescu, TU Bucharest

13:00 Simulation of Quantum Transport in Small Semiconductor Devices (Invited)
2-1 M. V. Fischetti1, S.E. Laux2, and A. Kumar2

1Univ. of Massachusetts and 2IBM, USA
13:30
 Gate Tunneling Current Fluctuations Associated with Random Dopant Effects
2-2 S. Toriyama1, K. Matsuzawa1, and N. Sano2

1Toshiba and 2Univ. of Tsukuba, Japan
13:50
 Intrinsic Parameter Fluctuations in MOSFETs Due to Structural Non-Uniformity of High-ƒÈ Gate Stack Materials
2-3 A.R. Brown1, J.R. Watling1, A. Asenov1, G. Bersuker2, and P. Zeitzoff2

1Univ. of Glasgow, UK and 2SEMATECH, USA
14:10
 Effect of Discrete Dopant Distribution on MOSFET Scaling into the Future
2-4 Y. Ashizawa and H. Oka

Fujitsu Labs., Japan
14:30 Efficient Calculation of Quasi-Bound State Tunneling in CMOS Devices
2-5 M. Karner, A. Gehring, H. Kosina, and S. Selberherr

Technical Univ. Vienna, Austria
14:50 Statistics of Grain Boundaries in Gate Poly-Si
2-6 H. Watanabe

Toshiba, Japan

15:10   Break


Session 3:   SOI Devices (Diamond Room)
Chairpersons: N. Goldsman, Univ. of Maryland

K. Ishikawa, Renesas Technol.

15:30 Investigation of 6T SOI SRAM Cell Stability Including Quantum and Gate Direct Tunneling Effects by Three-Dimensional Devices Simulation
3-1 R. Tanabe, Y. Tosaka, Y. Ashizawa, and H. Oka

Fujitsu Labs., Japan
15:50
 DGSOI versus Bulk: A Quantum-Ballistic Study of 25nm nMOSFETs
3-2 A. Schenk1,2, F.O. Heinz3, and B. Schmithüsen1

1Swiss Fed. Inst. of Technol., 2Synopsys Switzerland, Switzerland, and 3Intel, USA
16:10
 Device Behavior Modeling for Carbon Nanotube Silicon-on-Insulator MOSFETs
3-3 A. Akturk, G. Pennington, and N. Goldsman

Univ. of Maryland College Park, USA
16:30
 Simulaiton Study of Reduced Self-Heating in Novel Thin-SOI Vertical Bipolar Transistors
3-4 Qiqing (Christine) Ouyang and K. Xiu

IBM, USA
16:50 Implementation of ESD Protection in SOI Technology: A Simulation Study
3-5 V. Axelrad1, A. Shibkov1, H. Hayashi2, and K. Fukuda2

1SEQUOIA Design Systems, USA and 2Oki Electric, Japan
17:10 An Accurate Separation of Floating-Body and Self-Heating Effects for High-Frequency Characterization of SOI MOSFET's
3-6 N. Miura, T. Chiba, and S. Baba

Oki Electric, Japan

18:00   Reception (Hohoh Room, 3F)



Friday, September 2

Session 4:   Process Modeling (Diamond Room)
Chairperson: T. Iwasaki, Hitachi

9:00 Molecular Dynamics Simulation of Plasma-Surface Interactions during Dry Etching Processes (Invited)
4-1 S. Hamaguchi

Osaka Univ., Japan
9:30
 Atomistic Modeling Accounting for Retardation of Boron Diffusion and Dominant BmIn Clusters in Pre-Dopen Silicon
4-2 J.-H. Yoo, C.-O. Hwang, and T. Won

Inha Univ., Korea
9:50
 Modeling Dopant Diffusion in Strained and Strain-Relaxed Epi-SiGe
4-3 Y.M. Sheu1, T.Y. Huang1, Y.P. Hu1, C.C. Wang1, S. Liu1, R.Duffy2, A. Heringa2, F. Roozeboom3, N.E.B. Cowern4, and P.B. Griffin5

1TSMC, Taiwan, 2Philips Research Leuven, Belgium, 3Philips Research Labs. Eindhoven, Netherlands, 4Univ. of Surrey, UK, and 5Stanford Univ., USA
10:10
 Arsenic Diffusion in the Presence of Germanium in Si using First Principles Studies
4-4 J. Zhang1, Y. Ashizawa2, and H. Oka2

1Fujitsu R&D Center, China and 2Fujitsu Labs., Japan

10:30   Break


Session 5:   CNT and Widegap (Diamond Room)
Chairperson: Y. Oda, Matsushita Electric Industrial

10:50 A Schrödinger-Poisson Solution of CNT-FET Arrays
5-1 A. Marchi, S. Reggiani, and M. Rudan

Univ. of Bologna, Italy
11:10
 Low-Field Transport Model for Semiconducting Carbon Nanotubes
5-2 G. Pennington, A. Akturk, and N. Goldsman

Univ. of Maryland, USA
11:30
 Geometry-dependence of the DC and AC Response of Ohmic Contact Carbon nanotube Field Effect Transistors
5-3 M. Pourfath1, B.H. Cheong2, W.J. Park2, and H. Kosina1

1Technical Univ. Vienna, Austria and  2Samsung Advanced Inst. of Technol., Korea
11:50
 Characterization of 4H-SiC MOSFET Interface Trap Charge Density Using a First Principles Coulomb Scattering Mobility Model and Device Simulation
5-4 S. Potbhare1, G. Pennington1, N. Goldsman1, J.M. McGarrity1, and A. Lelis2

1Univ. of Maryland and 2U.S. Army Research Labs., USA.


Session 6:   Device Applications (Hohoh Room, 3F)
Chairperson: K. Matsuzawa, Toshiba

10:50 ESD Protection Design Optimization Using a Mixed-Mode Simulation and Impact on ESD Protection Design of Power Line Resistance
6-1 H. Hayashi, T. Kuroda, K. Kato, K. Fukuda, S. Baba, and Y. Fukuda

Oki Electric, Japan
11:10
 Three Diminsional CMOS Image Sensor Cell Simulation and Optimization
6-2 K.-H. Paik, S.-H. Lee, J.-H. Lyu, K.-H. Lee, Y.-K. Park, and J.-T. Kong

Samsung Electronics, Korea
11:30
 Time-Domain-Based Modeling of Carrier Transport in Lateral p-i-n Photodiode
6-3 G. Suzaki, K. Konno, D. Navarro, N. Sadachika, Y. Mizukane, O. Matsushima, and M. Miura-Mattausch

Hiroshima Univ., Japan
11:50
 Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond
6-4 X. Qi, A. Gyure, Y. Luo, S.C. Lo, and M. Shahram

Synopsys, USA

12:10   Lunch


Session 7:   Device Characterization (Diamond Room)
Chairpersons: K. Mayaram, Oregon State Univ.

M. Miura-Mattausch, Hiroshima Univ.

13:30 Coupled Simulation of Device Performance and Heating of Vertically Stacked Three-Dimensional Integrated Circuits
7-1 A. Akturk1, N. Goldsman1, and G. Metze2

1Univ. of Maryland College Park and 2Lab. of Physical Sciences, USA
13:50
 A Physics-Based TCAD Framework for the Noise Analysis of RF CMOS Circuits under the Large Signal Operation
7-2 S. Hong1, R. Kim1, C.H. Park2, H.S. Min1, and Y.J. Park1

1Seoul National Univ. and  2Kwangwoon Univ,. Korea
14:10
 Compact Modeling of Source-Side Injection Programming for 90nm-Node AG-AND Flash Memory
7-3 K. Sonoda1, S. Narumi1, M. Tanizawa1, K. Ishikawa1, H. Kurata2, T. Eimori1, and Y. Ohji1

1Renesas Technol. and 2Hitachi, Japan
14:30
 Integrated Simulation Flow for Self-Consistent Manufacturability and Circuit Performance Evaluation
7-4 A. Shibkov and V. Axelrad

SEQUOIA Design Systems, USA
14:50 A Statistical Unified Model for Inter-Die and Intra-Die Process Variation
7-5 J.-S. Doh, D.-W. Kim, S.-H. Lee, J.-B. Lee, Y. Park, M.-H. Yoo, and J.-T. Kong

Samsung Electronics, Korea
15:10 A Highly Efficient Statistical Compact Model Parameter Extraction Scheme
7-6 K. Takeuchi and M. Hane

NEC Corp., Japan


Session 8:   Simulation Techniques (Hohoh Room, 3F)
Chairpersons: T. Grasser, Technical Univ. Vienna

M. Kimura, Sony

13:30 Phenomenological Model for "Stress Memorization" from a Capped Poly Process
8-1 L.S. Adam, C. Chiu, M. Huang, Y. Wang, and J. Wu

Texas Instruments, USA
13:50
 The Impact of Layout on Stress-Enhanced Transistor Performance
8-2 V. Moroz1, G. Eneman2,3, P. Verheyen2, F. Nouri4, L. Washington4, L. Smith1, M. Jurczak2, and D. Pramanik1

1Synopsys, USA, 2IMEC, 3K.U. Leuven, ESAT-INSYS, Belgium, and  4Applied Materials, USA
14:10
 Dynamic Mesh Adaptation for Three-Dimensional Electromigration Simulation
8-3 W. Wessner, H. Ceric, J. Cervenka, and S. Selberherr

Technical Univ. Vienna, Austria
14:30
 First-Principle Computation of Relaxation Times in Semiconductors for Low and High Electric Fields
8-4 S.C. Brugger and A. Schenk

ETH Zürich, Switzerland
14:50 On the Tunneling Energy within the Full-Band Structure Approach
8-5 F.M. Bufler and A. Schenk

ETH Zürich and Synopsys Schweiz GmbH, Switzerland
15:10 Effects of Local Electric Field and Effective Tunnel Mass on the Simulation of Band-to-Band Tunnel Diode Model
8-6 K.R. Kim and R.W. Dutton

Stanford Univ., USA


15:30-18:30   Poster Session (Diamond Room, Exhibition Space)

P-1 One-Dimensional Corrected Drift-Diffusion Model: McKelvey's Method Extended with Accelerated-Multi-Flux

M. Hogyoku

Seiko Epson, Japan
P-2 Threshold Voltage Model of Single Gate SOI MOSFETs Derived from Asymptotic Method

J. Aoyama1, T. Takani1, T. Toyabe1, and L. Kalachev2

1Toyo Univ., Japan and  2Univ. of Montana, USA
P-3 Physical Modelling and Scaling Properties of 4H-SiC Power Devices

T. Hatakeyama, C. Ohta, J. Nishio, and T. Shinohe

Toshiba, Japan
P-4 Simulation of Spin Polarized Transport in GaAs/GaAlAs Quantum Well Considering Intersubband Scattering by Monte Carlo Method

L. Kong, X. Liu, G. Du, Y. Wang, J. Kang, and R. Han

Peking Univ., China
P-5 Performance Analysis of Novel 600V Super-Junction Power LDMOS Transistors with Embedded p-Type Round Pillars

K. Permthammasin1, G. Wachutka1, M. Schmitt2, and H. Kapels2

1Munich Univ. of Technol. and 2Infineon Technols., Germany
P-6 Three-Dimensional Simulation of Stress Dependent Thermal Oxidation

C. Hollauer, H. Ceric, and S. Selberherr

Technical Univ. Vienna, Austria
P-7 Application of Three-Dimensional Topography Simulation in the Design of Interconnect Lines

A. Sheikholeslami1, F. Parhami2, R. Heinzl1, E. Al-Ani1, C. Heitzinger1, F. Badrieh2, H. Puchner2, T. Grasser1, and S. Selberherr1

1Technical Univ. Vienna, Austria and 2Cypress Semicon., USA
P-8 Monte Carlo Simulation of Ion Implantation for Doping of Strained Silicon MOSFETs

R. Wittmann1, A. Hossinger2, and S. Selberherr1

1Technical Univ. Vienna, Austria and 2SILVACO Technol. Center, UK
P-10 A 3D Charge Model for FinFETs with Ballistic Transport

D. Zhang, X. Shao, Z. Yu, and L. Tian

Tsinghua Univ., China
P-11 Simulaiton of Drain Current Reduction Caused by Process-Induced Stress

T. Uchida, H. Takashino, M. Tanizawa, T. Okagaki, K. Ishikawa, T. Eimori, and Y. Ohji

Renesas Technol., Japan
P-12 A Fast Algorithm for 3-D Inductance Extraction Based on Investigation of Open-Circuit Current

H. Wei, W. Yu, and Z. Wang

Tsinghua Univ., China
P-13 Modeling of Energy Capability of Power Devices with Copper Layer Integration

B. Elattari1, G. Van den bosch1, T. Webers1, P. Moens2, and G. Groeseneken1,3

1IMEC, 2AMI Semicon. Belgium, and 3KULeuven, Belgium
P-14
 Generalized Comprehensive Approach for Robust Three-Dimensional Mesh Generation for TCAD

R. Heinzl and T. Grasser

Technical Univ. Vienna, Austria
P-15
 Comparison of Different Approaches for the Simulation of Topography Evolution during Lithography Development Steps

T. Schnattinger and E. Bär

Fraunhofer Inst. of Integrated Systems and Device Technol., Germany
P-16
 Modeling of Tunneling Currents for Highly Degraded CMOS Devices

R. Entner, A. Gehring, H. Kosina, T. Grasser, and S. Selberherr

Technical Univ. Vienna, Austria
P-17
 Numerical and Analytical Modeling of the High-Field Electron Mobility in Strained Silicon

S. Dhar, G. Karlowatz, E. Ungersboeck, and H. Kosina

Technical Univ. Vienna, Austria
P-18
 Computer Simulation of Germanium Nanowire Field Effect Transistors

Y. Li1,2, J.-W. Lee2, W.-H. Chen2, B.-S. Lee3, and C.-S. Lu2

1National Nano Device Labs., 2National Chiao Tung Univ., and 3National Central Univ., Taiwan
P-19
 Analysis and Simulation of Self-Heating Effects in RF LDMOS Devices

M. A. Belaïd, K. Ketata, H. Maanane, and M. Gares

Univ. of Rouen, France
P-20
 Coupling Three-Dimensional Mesh Adaptation with an A Posteriori Error Estimator

P. Schwaha, R. Heinzl, M. Spevak, and T. Grasser

Technical Univ. Vienna, Austria
P-21
 Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer Regime

X. Wang, P. Oldiges, A. Bryant, J. Cai, Qiqing (Christine) Ouyang, and K. Rim

IBM, USA
P-22
 Linearity Analysis of RF LDMOS Devices Utilizing Harmonic Balance Device Simulation

O. Tornblad1, C. Ito2, F. Rotella3, G. Ma1, and R.W. Dutton4

1Infineon Technols. North America, 2LSI Logic, 3Fujitsu Labs. of America, and 4Stanford Univ., USA
P-23
 Doping Profile Effects on Device Characteristics of Nano-Scale MOSFETs

H. Takeda and N. Mori

Osaka Univ., Japan
P-24
 Quantum Effects Incorporation into Monte Carlo Device Simulators for Modeling Nano-Scale Alternative Device Technologies

D. Vasileska1, S.S. Ahmed2, and C. Ringhofer1

1Arizona State Univ. and 2Purdue Univ., USA
P-25
 Forward Body-biased Single Halo MOS Devices for Low Voltage Analog Circuits

K. Narasimhulu and V.R. Rao

Indian Inst. of Technol. Bombay, India
P-26
 Study of RF Performance for Graded-Channel SOI MOSFETs

W. Ma and S. Kaya

Ohio Univ., USA
P-27
 A Novel Single-Gated Strained CMOS Architecture: COSMOS

A. Al-Ahmadi and S. Kaya

Ohio Univ., USA



Saturday, September 3

Session 9:   Nano-Devices (Diamond Room)
Chairperson: Y. Ohkura, Selete

9:00 Physics and Performance of Phase Change Memories (Invited)
9-1 A. Lacaita

Politecnico di Milano, Italy
9:30
 Atomistic Modeling of Electron Transport in Self-Assembled Arene-Based Molecular Wires
9-2 X.-Y. Liu1, J.E. Raynolds2, C. Wells2, J. Welch2, and T.S. Cale1

1Rensselaer Polytechnic Inst. and 2Univ. at Albany-SUNY, USA
9:50
 Electro-Thermal Simulations of Nanoscale Transistors with Optical and Acoustic Phonon Heat Conduction
9-3 J.-H. Chun, B. Kim, Y. Liu, O. Tornblad, and R.W. Dutton

Stanford Univ., USA
10:10
 Comprehensive Numerical Model for Phase-Change Memory Simulations
9-4 A. Redaelli1, A.L. Lacaita1, A. Benvenuti2, and A. Pirovano2

1Politecnico di Milano and 2STMicroelectronics, Italy

10:30   Break


Session 10:   Muti-Gate Transistors (Diamond Room)
Chairperson: S. Odanaka, Osaka Univ.

10:50 FinFET Source/Drain Profile Optimization Considering GIDL for Low Power Applications
10-1 K. Tanaka, K. Takeuchi, and M. Hane

NEC Corp., Japan
11:10
 A 3-Dimensional Particle Device Simulator; HyDeLEOSMC and Its Application to a FinFET
10-2 Y. Ohkura, C. Suzuki, T. Enda, H. Takashino, H. Ishikawa, T. Kojima, and T. Wada

Selete, Japan
11:30
 A Quantum-Mechanical Analysis of the Electrostatics in Multi-Gate FETs
10-3 E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani

Univ. of Bologna, Italy
11:50
 A Full Newton Scheme for the Coupled Schrödinger, Poisson, and Density-Gradient Equations
10-4 S. Jin, Y.J. Park, and H.S. Min

Seoul National Univ., Korea

12:10   Lunch


Session 11:   Strained Devices 1 (Diamond Room)
Chairpersons: M. Ogawa, Kobe Univ.

G. Wachutka, Munich Univ. of Tech.

13:30 Monte-Carlo Simulations of Performance Scaling in Strained-Si nMOSFETs
11-1 A. Kumar1, M.V. Fischetti2, and S.E. Laux1

1IBM and 2Univ. of Massachusetts, USA
13:50
 A New Quasi Ballistic Model for Strained MOSFET
11-2 E. Fuchs1,2,3, S. Orain4, C. Ortolland4,5, P. Dollfus2, G. Le Carval3, D. Villanueva4, A. Dray1, H. Jaouen1, and T. Skotnicki1

1ST Microlelectronics, 2IEF, CNRS-Univ. Paris 11, 3CEA LETI/D2NT/LSCDP, 4Philips Semicon., and 5LPM, UMR CNRS 5511, France
14:10
 Joule Heating under Quasi-Ballistic Transport Conditions in Bulk and Strained Silicon Devices
11-3 E. Pop, J. Rowlette, R. Dutton, and K. Goodson

Stanford Univ., USA
14:30
 The Effect of Degeneracy on Electron Transport in Strained Silicon Inversion Layers
11-4 E. Ungersboeck and H. Kosina

Technical Univ. Vienna, Austria
14:50