SISPAD 2003--Call for Papers

CALL FOR PAPERS

2003 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES: SISPAD 2003

September 3-5, 2003 • Boston Marriott Cambridge • Cambridge • MA • USA

Conference Chair
Paco Leon
MT Associates

Technical Committee Chair
Phil Oldiges
IBM Corporation

Technical Committee Members:

A. Alam (Agere, USA)
G. Baccarani (Univ. Bologna, Italy)
T. Cale (RPI, USA)
C. Dai (Intel, USA)
C. Diaz (TSMC, Taiwan)
M. Duane (Applied Materials, USA)
S. Dunham (Univ. Washington, USA)
N. Goldsman (Univ. Maryland, USA)
S. Ho (Hitachi, Japan)
K. Ishikawa (Mitsubishi, Japan)
S. Ito (Toshiba, Japan)
S. Jones (Bookham, UK)
E. Kan (Cornell Univ., USA)
M. Kimura (Sony, Japan)
Z. Krivokapic (AMD, USA)
J. Kuo (Univ. Waterloo, Canada)
J. Lorenz (Fraunhofer Institute, Germany)
K. Mayaram (Oregon State Univ., USA)
C. Mouli (Micron, USA)
S. Odanaka (Univ. Osaka, Japan)
M. Orlowski (Motorola, USA)
W. Schoenmaker (IMEC, Belgium)
S. Selberherr (TU Vienna, Austria)
G. Wachutka (TU Munich, Germany)

Under the sponsorship of the Electron Devices Society of the IEEE, an international conference on the numerical modeling of semiconductor devices, processes and equipment for integrated circuits will be held in Cambridge, Massachusetts on September 3-5, 2003.
This meeting provides an opportunity for the presentation and discussion of recent advances in modeling and simulation of semiconductor devices, processes and equipment for increased understanding and for applications to both design and manufacturing. The program consist of 20-minute presentations, with ample time for questions and answers. A poster session is also planned, which provides for a less formal venue and allows for more in-depth interactions with the authors. The presentations will be selected from two-page abstracts of topics which may include:

All aspects of device simulation, including transport in nano-structures, models of VLSI device scaling limits, quantum effects, and novel devices.
All aspects of process simulation, including both continuum and atomistic approaches.
Equipment, topography, and lithography simulation.
Interconnect modeling and algorithms.
Compact device modeling for circuit simulation; integration of circuit and device simulation.
User interfaces and visualization.
High performance computing, numerical methods and algorithms, including gridding.
Simulations of such devices as microsensors, microactuators, optoelectronics devices, lasers, and flat panel displays.
Benchmarking, calibration, and verification of simulators.

Deadline for submission of abstracts: Feb. 28, 2003
Authors should submit 27 copies of a two-page (double-sided) abstract including figures to:
SISPAD 2003 Conference Manager CISX 332 Stanford University Stanford, CA 94305-4075 Email: sispad03@gloworm.stanford.edu Phone: (650)723-1349; Fax:(650)725-7731

The abstract should include: (1)title, (2)first author's name and complete mailing address, (3)names and affiliations of additional authors, and (4)electronic mailing address. Authors will be notified of the Technical Program Committee's decision by May 2, 2003.
Authors of accepted papers will be instructed on how to prepare a final extended abstract for inclusion in the 2003 SISPAD Proceedings.
Selection Criteria: The degree to which the two-page abstract deals with the following criteria will strongly affect whether the paper is selected: 1) What is the motivation for your paper? 2) What is new or original and how does it differ from previous work? 3) What is its impact or significance? 4) What are the major and specific results?
More information about SISPAD 2003 can be found at: www-tcad.stanford.edu/sispad03.
Companion workshop to be held at MIT on Saturday, Sept. 6, 2003:

"Modeling and Simulation Issues in Strained Si MOSFETs"
Organizers: Judy Hoyt; Dimitri Antoniadis, MIT
The goal of this workshop is to provide a forum to discuss key modeling and simulation issues relevant to strained Si MOSFETs.Topics include introductory overviews of the technology, including fundamental materials and device reviews, strained Si, SiGe, and SiGeC energy band structure, carrier transport, process modeling (e.g. dopant and Ge diffusion), stress modeling in complex device structures, and self-heating.

	2003 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES: SISPAD 2003 September 3-5, 2003 • Boston Marriott Cambridge • Cambridge • MA • USA
Conference Chair Paco Leon MT Associates Technical Committee Chair Phil Oldiges IBM Corporation Technical Committee Members: A. Alam (Agere, USA) G. Baccarani (Univ. Bologna, Italy) T. Cale (RPI, USA) C. Dai (Intel, USA) C. Diaz (TSMC, Taiwan) M. Duane (Applied Materials, USA) S. Dunham (Univ. Washington, USA) N. Goldsman (Univ. Maryland, USA) S. Ho (Hitachi, Japan) K. Ishikawa (Mitsubishi, Japan) S. Ito (Toshiba, Japan) S. Jones (Bookham, UK) E. Kan (Cornell Univ., USA) M. Kimura (Sony, Japan) Z. Krivokapic (AMD, USA) J. Kuo (Univ. Waterloo, Canada) J. Lorenz (Fraunhofer Institute, Germany) K. Mayaram (Oregon State Univ., USA) C. Mouli (Micron, USA) S. Odanaka (Univ. Osaka, Japan) M. Orlowski (Motorola, USA) W. Schoenmaker (IMEC, Belgium) S. Selberherr (TU Vienna, Austria) G. Wachutka (TU Munich, Germany)	Under the sponsorship of the Electron Devices Society of the IEEE, an international conference on the numerical modeling of semiconductor devices, processes and equipment for integrated circuits will be held in Cambridge, Massachusetts on September 3-5, 2003. This meeting provides an opportunity for the presentation and discussion of recent advances in modeling and simulation of semiconductor devices, processes and equipment for increased understanding and for applications to both design and manufacturing. The program consist of 20-minute presentations, with ample time for questions and answers. A poster session is also planned, which provides for a less formal venue and allows for more in-depth interactions with the authors. The presentations will be selected from two-page abstracts of topics which may include: All aspects of device simulation, including transport in nano-structures, models of VLSI device scaling limits, quantum effects, and novel devices. All aspects of process simulation, including both continuum and atomistic approaches. Equipment, topography, and lithography simulation. Interconnect modeling and algorithms. Compact device modeling for circuit simulation; integration of circuit and device simulation. User interfaces and visualization. High performance computing, numerical methods and algorithms, including gridding. Simulations of such devices as microsensors, microactuators, optoelectronics devices, lasers, and flat panel displays. Benchmarking, calibration, and verification of simulators. Deadline for submission of abstracts: Feb. 28, 2003 Authors should submit 27 copies of a two-page (double-sided) abstract including figures to: SISPAD 2003 Conference Manager CISX 332 Stanford University Stanford, CA 94305-4075 Email: sispad03@gloworm.stanford.edu Phone: (650)723-1349; Fax:(650)725-7731 The abstract should include: (1)title, (2)first author's name and complete mailing address, (3)names and affiliations of additional authors, and (4)electronic mailing address. Authors will be notified of the Technical Program Committee's decision by May 2, 2003. Authors of accepted papers will be instructed on how to prepare a final extended abstract for inclusion in the 2003 SISPAD Proceedings. Selection Criteria: The degree to which the two-page abstract deals with the following criteria will strongly affect whether the paper is selected: 1) What is the motivation for your paper? 2) What is new or original and how does it differ from previous work? 3) What is its impact or significance? 4) What are the major and specific results? More information about SISPAD 2003 can be found at: www-tcad.stanford.edu/sispad03. Companion workshop to be held at MIT on Saturday, Sept. 6, 2003: "Modeling and Simulation Issues in Strained Si MOSFETs" Organizers: Judy Hoyt; Dimitri Antoniadis, MIT The goal of this workshop is to provide a forum to discuss key modeling and simulation issues relevant to strained Si MOSFETs.Topics include introductory overviews of the technology, including fundamental materials and device reviews, strained Si, SiGe, and SiGeC energy band structure, carrier transport, process modeling (e.g. dopant and Ge diffusion), stress modeling in complex device structures, and self-heating.

sispad03@gloworm.stanford.edu