Wednesday, September 4

9:00

Opening and Welcome Remarks

S. Odanaka, Osaka Univ.

9:10

1-1

Plenary: What is Interesting Now and Future in Microscopic

Carrier Transport ?

T. Ando

Tokyo Inst. of Technol., Japan

9:55

1-2

Plenary: Integrated TCAD and ECAD Solutions - A Paradigm Shift

S.-W. Lee

Intel, USA

10:40

1-3

Plenary: Coupled-Field Modeling of Microdevices and Microsystems

G. Wachutka

Technische Univ. Muenchen, Germany

12:45

2-1

Surface Mobility in Silicon at Large Operating Temperature (Invited)

G. Baccarani

Univ. of Bologna, Italy

13:20

2-2

Simulation of DGSOI MOSFETs with a Schrodinger-Poisson Based Mobility Model

A. Schenk and A. Wettstein*

Swiss Fed. Inst. of Technol. and *Integrated Systems Eng.,

Switzerland

13:40

2-3

Ensemble Monte Carlo/Molecular Dynamics Simulation of Inversion Layer Mobility in Si MOSFETs -Effects of Substrate Impurity

Y. Kamakura, H. Ryouke and K. Taniguchi

Osaka Univ., Japan

14:00

2-4

Investigation of the Electron Mobility in Strained Si_1-xGe_x

at High Ge Composition

S. Smirnov, H. Kosina and S. Selberherr

Technical Univ. Vienna, Austria

14:35

3-1

A Strategy for Enabling Predictive TCAD in Development of Sub 100nm CMOS Technologies (Invited)

C. Machala, S. Chakravarthi, D. Li*, S.-H. Yang and

C. Chidambaram

Texas Instruments and *University of Texas, USA

15:10

3-2

On the Optimal Shape and Location of Silicided Source and Drain Contacts

P. Oldiges, C. Murthy, X. Wang, S. Fung and R. Purtell

IBM, USA

15:30

3-3

GIDL Simulation and Optimization for 0.13μm/1.5V Low Power CMOS Transistor Design

S. Zhao, S. Tang, M. Nandakumar, D.B. Scott, S. Sridhar,

A. Chatterjee, Y. Kim, S.-H. Yang, S.-C. Ai and S.P. Ashburn

Texas Instruments, USA

15:50

3-4

TCAD Driven Drain Engineering for Hot Carrier Reduction of 3.3V I/O PMOSFET

N. Miura, H. Hayashi, H. Komatsubara, M. Mochizuki and

K. Fukuda

Oki Electric, Japan

16:25

4-1

Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients

D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka,

H. Kawano, H. Ueno, M. Miura-Mattausch, H.J. Mattausch,

S. Kumashiro*, T. Yamaguchi*, K. Yamashita* and

N. Nakayama*

Hiroshima Univ. and *STARC, Japan

16:45

4-2

2D Simulation of a Buried-Heterostructure Tunable Twin-Guide DFB Laser Diode

L. Schneider, A. Witzig, A. Bregy, B. Schmidt*, M. Streiff,

M. Pfeiffer and W. Fichtner

ETH Zurich and *Nortel Networks Optical Components,

Switzerland

17:05

4-3

A Comprehensive Simulation Study on Strained-Si/SiGe nMODFET Scaling for RF Applications

Q.C. Ouyang, S.J. Koester, J.O. Chu, A. Grill, S. Subbanna

and D.A. Herman Jr.

IBM, USA

17:25

4-4

Realistic Scaling Scenario for Sub-100nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation

Y. Tsukamoto, T. Kunikiyo, K. Nii, H. Makino, S. Iwade,

K. Ishikawa and Y. Inoue

Mitsubishi Electric, Japan

9:00

5-1

On the Large-Signal CMOS Modeling and Parameter Extraction for RF Applications (Invited)

M. Je, I. Kwon, J. Han, H. Shin and K. Lee

KAIST, Korea

9:35

5-2

Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications

S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama,

M. Miura-Mattausch and H.J. Mattausch

Hiroshima Univ., Japan

9:55

5-3

The Physical Phenomena Responsible for Excess Noise in Short-Channel MOS Devices

R. Navid and R.W. Dutton

Stanford Univ., USA

10:15

5-4

Simulation of Substrate Currents

W. Schoenmaker, P. Meuris, W. Magnus and B. Maleszka

IMEC, Belgium

10:50

6-1

Multiscale Simulation of Diffusion, Deactivation, and Segregation of

Dopants - Ab-Initio to Continuum (Invited)

W. Windl

Ohio State Univ., USA

11:25

6-2

Integrated Atomistic Process and Device Simulation of Decananometre MOSFETs

A. Asenov, M. Jaraiz*, S. Roy, G. Roy, F. Adamu-Lema,

A.R. Brown, V. Moroz** and R. Gafiteanu**

Univ. of Glasgow, UK, *Univ. de Valladolid, Spain and

**Avant!, USA

11:45

6-3

3D MOSFET Simulation Considering Long-Range Coulomb Potential Effects for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Process Simulator

T. Ezaki, T. Ikezawa, A. Notsu, K. Tanaka and M. Hane

NEC, Japan

12:05

6-4

Transistor Width Dependence of LER Degradation to CMOS Device Characteristics

J. Wu, J. Chen and K. Liu

Texas Instruments, USA

13:40

7-1

Enhanced Advancing Front Delaunay Meshing in TCAD

P. Fleischmann and S. Selberherr

Technical Univ. Vienna, Austria

14:00

7-2

In-Advance CPU Time Analysis for Monte Carlo Device Simulations

C. Jungemann and B. Meinerzhagen

Univ. of Bremen, Germany

14:20

7-3

An Efficient Algorithm for 3D Interconnect Capacitance Extraction Considering Floating Conductors

O. Cueto, F. Charlet and A. Farcy*

CEA and *STMicroelectronics, France

14:55

8-1

System Level Model of Damping Effects for Highly Perforated Torsional Structures

G. Schrag, R. Sattler and G. Wachutka

Munich Univ. of Technol., Germany

15:15

8-2

A Novel CDM-Like Discharge Effect During Human Body Model (HBM) ESD Stress

V. Axelrad, Y. Huh*, J.W. Chen* and P. Bendix*

Sequoia Design Systems and *LSI Logic, USA

15:35

8-3

Simulation Technique of Heating by Contact Resistance for ESD Protection Device

K. Matsuzawa, H. Kawashima, T. Matsuhashi and S. Yasuda

Toshiba, Japan